Assignment title: Information
Assignment 1
Description Marks out of Wtg(%) Due date
Assignment 1 200 20 19 August 2016
Part A: Astable and Switching (4%)
(1) Astable
Use a single 4528 dual monostable to construct an astable circuit with a mark-space ratio of
0.33 and times of the order of 1 to 2 seconds. Put indicating LEDs on the circuit to indicate
both times.
Design hints
1. The final transition of the times pulse from one monostable may be used to trigger the
other monostable, producing waveforms as shown:
2. Mark-space means high time to low time.
3. You will need to look up the data for the I.C. you are using since details of timing
relationships are different for each (see data sheets).
Report
Provide all calculations and full final circuit schematic diagram.(2) MOSFET Switching
Find out information on the operation of, and configuring of, MOSFETs to be used in
switching circuits. In particular note the differences between BJTs and MOSFETs in this
role. Draw up a table to highlight the differences and hence the pros and cons on each
device for particular situations (eg. Switching high-to-low or low-to-high (ie. P or N type),
high or low current switching, low or high voltage switching).
Consider the following BJT switching circuit. Analyse the operation of the circuit to
understand the parameters involved. Choose suitable replacement MOSFETs to be used
instead of the output switching BJTs in the given circuit. Include any necessary circuit
changes for the new devices to operate so as to maintain the circuit's required parameters.
Calculate the power dissipation of the device(s) when ON.
Note that the input logic levels "0" and "1" are 0V and 5V respectively.
Where Vcc = 12V and Relay resistance = 18Ω .Part B: Power Transistor amplifier design (7%)
Design
Design a push-pull amplifier using the circuit arrangement given and with the
following specifications:
Supply voltages ± X V
Output power Y W
Voltage gain > Z dB
Low frequency roll-off point < Q Hz (Lower bandwidth limit)
Rin > J ohms
[Specifications (X,Y,Z,Q, J) will be individualised to students on StudyDesk]
Show all calculations for component values from DC and AC considerations. Choose a suitable
input signal voltage to achieve the specification.
[See Design Assignment A, Part C for design tips]
Simulation
Use MICROCAP (or similar) to simulate your design, using any suitable transistors
(e.g. Q1).
1. Plot transient analysis of output (on load resistor) and input (to C1). You should expect to
see a voltage gain >5 without distortion to the output sine waveform (ie: no clipping).
2. Short out the diode and R4 and repeat the transient analysis. Crossover distortion should be
more visible.
3. Determine the d.c. bias values at the base, collector and emitter of Q3 and at the common
emitter of the output stage. If your circuit does not work as expected, this should point to
the errors.
4. Run an A.C. Analysis to confirm the gain and bandwidth requirements (ie: correct capacitor
choices).ELE2504 – Electronic design and analysis 4
Part C: Voltage controlled oscillator design (5%)
Circuit
The circuit given below generates a rectangular wave and a triangular wave whose frequency
is determined by a voltage applied to the input.
Circuit operation
Assume the transistor is off, i.e. V
o2 is LOW. Vo1 ramps downwards due to the integrator R3C.
Meanwhile, since V
+2 is a positive voltage, when Vo1 passes V+2, Vo2 changes to HIGH, the
transistor turns on and C discharges via R4 and the transistor. Hence Vo1 ramps up and the
cycle repeats.
Design task
Design a VCO (voltage controlled oscillator) using an LM324 quad op. amp.or
LM741 op. amp.s (refer to the data sheets):
[Specifications will be individualised to student on StudyDesk]
Example Design specification
V
DD 9V
Vin
range 2V to 6V
Frequency range 100Hz – 300Hz
Duty cycle D:1 (high to low) 3:1
Vo
1 range 2 to 7V
A full analysis of the circuit operation and a design example follow.ELE2504 – Electronic design and analysis 5
1 1
2
2
Test
Assemble your design and check that it works. An LM324 (single supply) op. amp. and any
small transistor should work. You will also need to provide VDD / 2 with a voltage divider of
two 1k ohm resistors or similar.
If you have access to equipment, measure the performance of your circuit in regard to each of
the design specifications.
Analysis
Op. amp. A1 operates an integrator with an input voltage Vin / 2 set by the voltage divider
R
1 and R2. When TR1 is off, A1 integrates by charging C via R3 (pushing current into the left
hand side of C for positive Vin). When TR1 is on, C discharges to ground via R4.
By the principle that for an active op. amp., V+ = V–, and since V+ is held at Vin / 2:
a. When TR1 is off, current into C, = I1:
I
V
in Vin / 2
R
3
I Vin
2R
3
and hence V
o1 ramps downwards at a rate of:
V
in
2R
3C
b. When TR1 is on, current out of C via:
R
4 I2
I Vin
2R
4
but in this case since V– is still at V
in / 2, current is still also charging C via R3. So we
have:
I Vin
2R4ELE2504 – Electronic design and analysis 6
So the net current outflow from C is I
2 – I1.
Now A
2 acts as a comparator and its output switches TR1 when Vo1 reaches some fraction
(say β) of Vo2 which can be assumed to switch between zero and VDD.
Define R5
R
5 R6
V
DD VDD
When V
o2 is VDD , then V2 (
2
)
2
1 VDD
2
V
DD VDD
When V
o2 is zero, then V2 (
2
)
2
1 VDD
2
and these two voltages are the thresholds at which Vo1 causes switching.
The voltage Vo1 thus ramps up and down at different rates as shown:
So in order to achieve a duty cycle of D:1,
I
2 I1 I1
D
or D I2 I1 I1
DI
2 1 D I1
DVin
1 DVin
2R
4 R
2R
3
DR
3
4
1 DELE2504 – Electronic design and analysis 7
2
Timing
V V
During the time t1, the voltage at Vo1, Vo1(t) in DD 1
2R
3C 2
V
and at t
1, Vo1(t1) DD 1
2
Hence
VD
D 1 Vin t1 VDD 1
2 2R
3C 2
V 2R C
and so t1 DD 1 1 3
2
2V
DDR3C
V
in
V
in
Since t2 Dt1
t
2DV
DDR3C
V
in
1 D 2DVDDR C
and T 3
V
in
or f Vin
1 D 2VDDR3C
Design example
Choose R5 and R6
Vo
1 range is 2 to 7V
2 VDD 1
2
4.51
0.55
7 VDD 1
2
4.51
0.55
Choose resistors to be as large as possible consistent with the assumption that the current
into V
2+ is negligible, say:
R
5 = 100k Ω
R
6 = 82k ΩELE2504 – Electronic design and analysis 8
Frequency
Choose R
3 and C as a pair by trial and error until practical values of both are found.
f (min) 100 Hz
V
in (min) 2V
100 2
f (max) 300 Hz
V
in (max) 6V
300 6
4 2 9 0.55 R
3C
4
4 2 9 0.55 R
3C
Say
So
R
3C 5.0510
C 3.3 nF
R
3 150 k
R
4 112.5 k say 120 k
Transistor
Maximum current in transistor Vin (max) / 2
R4
33 A
Assume h
FE 100, so I B 0.3 A
Transistor is turned on when V
o2 9V
so R
7
8.3
0.3 A
25 M
Note this resistor is impractically large. So allow more base overdrive and choose
R
7 = 1 MΩ.
(The 33pF capacitor is to aid switching speed.)
Report
● Show all design calculations
● Show full circuit diagram with all component values
● Results from testing or simulation
● Comparison of results with specifications with observations and conclusions.ELE2504 – Electronic design and analysis 9
Part D: Semiconductor devices (4%)
Select two devices and submit a short report for each, covering the following details:
● what the device is (name, type)
● explanation of the devices' features and how it works
● sample circuit application making use of its feature(s) with a circuit operation
explanation (include any relevant calculations).
Device list:
2N4871
QED223
BPV11
1N6276CA (or 1.5KEI6CA)
IRF730
BUK854-500
V33ZA7 (GE-MOV)
BD333ELE2504 – Electronic design and analysis 10ELE2504 – Electronic design and analysis 11
Design assignment A
Description Marks out of Wtg(%) Due date
Design assignment A 0 0 Week 5
This assignment does not have to be submitted for marking. However it may be the subject of
a question in the examination.
Part A: Logic design
(1) Astable
Use a single 4528 dual monostable to construct an astable circuit with a mark-space ratio of
0.5 and times of the order of 1 to 2 seconds. Put indicating LEDs on the circuit to indicate
both times.
Design hints
1. The final transition of the times pulse from one monostable may be used to trigger the
other monostable, producing waveforms as shown:
2. Mark-space means high time to low time.
3. You will need to look up the data for the I.C. you are using since details of timing
relationships are different for each (see data sheets).
Test
Assemble the circuit and check that your design works.
Design a logic interface circuit to allow the connection of data from either of the two specific
logic gates shown (one TTL and one CMOS), to either of two other specific logic gates (TTL
and CMOS) as shown in the sketch.ELE2504 – Electronic design and analysis 12
(2) Logic Design & Family Compatibility
Specifications
1. Five volt power supplies are used on both source and destination circuits.
2. The signal must not be inverted in passing through the interface. (It may of course be
inverted within the interface, but must emerge the same as it went in.)
3. The interface is to contain an LED (with current between 5mA and 10mA) to indicate the
state of the data (at point X), as well as any extra gates (of any type) needed to provide the
interface function. (Use gates only, not transistors.)
4. The interface must be properly designed to ensure that it takes into account the worst
case specifications of the logic gates involved. D.C. design only is required.
Steps
1. Assemble the relevant worst case data on all gates and organise in a table of the
following form, using data @ 25°C.
Gate V
OH IOH VOL IOL VIH IIH VIL IIL
74HC00 – – – –
74S02 – – – –
4001 – – – –
74LS00 – – – –ELE2504 – Electronic design and analysis 13
2. Design the circuit by carefully considering each possible position of the switches, both
voltage and current and both high and low states, and choosing a combination of gates to
form the interface circuit.
Report
Submit a report containing at least the following:
1. Data for the gates in a table as above. (Data sheets at the end of this book.)
2. For the simple case of the interface being a direct connection, give clear consideration of
each possible combination of gates and logic levels, and identification of any problems.
Give reasons.
3. Your solution to the problems, including a sketch of the interface circuit and justification
of any resistor values.
Note
There is no need to assemble and test the circuit since most individual I.C.s
will perform better than the worst case figures indicate, and so a simple test
of operation would prove nothing.ELE2504 – Electronic design and analysis 14ELE2504 – Electronic design and analysis 15
Part B: Differential amplifier exercise
The circuit
Simulation
Use MICROCAP (or similar) to analyse the circuit. Leave out the voltage divider network
(47k, 10k, 47k) for this.
1. Determine the d.c. voltages at both collectors and at the common emitter, by grounding
the base of Q1 and running a d.c. analysis.
2. Determine the d.c. response at either collector to a varying input voltage over the range
–0.3v to +0.3v by adding a 1mV d.c. source as shown above and running a d.c. analysis.
Use limits as shown on next page.
3. Add a 1μf capacitor to the input and so determine a.c. voltage gain, Ad (single collector
to ground).
4. Connect the two bases together at the bias network and determine the a.c. common mode
gain (single collector to ground). Change sine source to 1V.
5. Add the constant current source shown below in place of the common emitter resistor RE
and again determine the single ended a.c. common mode gain. (i.e., repeat 4 above).
Notice that it is very frequency dependent, but for frequencies less than about 1MHz, it
is very much less than it was for the single resistor case. Hence common mode rejection
ratio is very much improved.ELE2504 – Electronic design and analysis 16
Help using MICROCAP
For determining the d.c. response at the collectors, try these analysis limits:
Sample plot ....ELE2504 – Electronic design and analysis 17
Test
1. Construct the circuit shown on the previous page.
2. Vary the potentiometer over its entire range and at about nine evenly spaced intervals
measure the voltage on the base and the voltage at both collectors.
You will need to take additional points at the cross-over to get a good representation
of the shape of the curves.
The following values of base voltage are suggested: –0.3, –0.1, –0.06, –0.03, 0, +0.03,
+0.06, +0.1, +0.3 volts.
3. Calculate the corresponding collector circuits.
4. Plot on the one set of axes, graphs of each collector current and the sum of the two,
versus input voltage.
Your graph should appear as sketched below.
Report
● Submit MCap schematic (with node numbers) and DC analysis plot.
● Submit table of results from practical testing with graph.ELE2504 – Electronic design and analysis 18
Part C: Transistor Amplifier Design
Design and test a common emitter amplifier using the circuit shown and the selected
specifications.
Specifications
Get your own specifications provided on the StudyDesk
Bandwidth > 100Hz → 20kHz
Design
(Example follows)
1. Allow about half V
CC across the transistor;
V
CE = 0.5 VCC
2. So the voltage across RC and RE is VCC – VCE
IC
(RE + RC) = VCC – VCE
3. Since the voltage gain will be very close to RC / RE,
R
C / RE = AV
Hence R
C and RE can be determined, choosing appropriate preferred values.ELE2504 – Electronic design and analysis 19
E
4. Determine:
VE
= I
CRE and hence
VB
= V
E + VBE
5. Choose R
1 and R2. The maximum value of base current is:
IB
(max) = IC / hfe (min)
Now let the current in R
1 and R2 (IDIV) be about 5 to 10 times IB, so
ID
IV = VCC / (R1 + R2) = say 10 IB (max) (1)
and since I
B can now be neglected relative to IDIV,
VB
= R
2 / (R1 + R2) × VCC (2)
Hence R
1 and R2 can be chosen using the nearest preferred values.
6. Check the design using the nominal preferred values to ensure that VCE ≈ 0.5VCC. If not,
modify R1 and R2 slightly, remembering that their ratio is important (equation (2) above)
but their absolute magnitude is not (equation (1) above).
Example
Voltage gain 7
V
CC 10v
I
C 2.5mA
Assume h
fe(min) 130.
1. V
CE = 0.5 VCC
= 5v
2. I
C (RE + RC) = VCC – VCE
2.5 × 10–3 (R + RC) = 5
3. R
C / RE = Av
= 7
So R
E + RC = 2k
R
C / RE = 7
∴ R
E
= 250 → 270Ω
R
C = 1750 → say 1800Ω
4. V
E = IC RE
= 2.5 × 10–3 × 270
= 0.68vELE2504 – Electronic design and analysis 20
V
B = VE + 0.7
≈ 1.4v
5. I
B (max) = IC / hfe (min)
= 2.5 × 103/130
= 19.2µA
ID
IV = say 10 × IB
= 192µA
R
1 + R2 = VCC / IDIV
= 10/192µA
= 52kΩ
V
B = R2 / (R1 + R2) × VCC
R
2 / (R1 + R2) = 1.4 / 10 = 0.14
or the voltage across R2 = 1.4v, and
the voltage across R1 = 8.6v.
∴ R
2
= 0.14 × 52k
= 7.3kΩ say 6.8kΩ (reducing ≈ 7%)
and R
1 = 0.86 + 52k
= 44.7kΩ, say 39kΩ (reducing ≈ 12.8%)
6. Check:
V
B = 6.8k / (39k + 6.8k) × 10v
= 1.5v
V
E = 0.8v
I
C = 0.8270
= 3.0mA
V
C = 10 – 3.0 × 1.8k
= 4.6v
∴ V
CE
= 4.6 – 0.8
= 3.68v
This is significantly less than 5v but could be acceptable. If not, select another R1 and R2
by trial and error. Try 8.2k and 56k which gives VB = 1.3v which is about as far off in the
opposite direction. This may be satisfactory if the amplifier is not required to handle
large signals. If not satisfactory, repeat until some satisfactory values are found.ELE2504 – Electronic design and analysis 21
Simulation
Use the circuit simulation programme MICROCAP (or similar) to analyse your design:
(Help is given on the following page.)
1. Determine the d.c. voltages at all points. This will check your design – if these are
correct, the circuit should amplify an a.c. signal. Check choice of C1 for specification.
2. Determine the frequency response (voltage gain and phase versus frequency) over the
range 1Hz to 1MHz.
3. Bypass RE with a capacitance of 0.47 µF and again determine the frequency response
over the same frequency range.
For example:
MICROCAP analysis of the example circuit above using transistor Q1, gives the frequency
response graph on the following page, using the analysis limits on the page after that.
Help using MICROCAP
The following may help to get the required results using MICROCAP:
● draw the circuit
● select VIEW, show node numbers and note the node numbers of the input before the
capacitor, and the output (collector)
● select RUN, Transient Analysis and set the Analysis Limits
● select AC Run and the result will be a frequency response graph.
Transient response – (time base)
Sample Analysis setup ...
Note that the node numbers in the 'Y expression' pertain to the nodes on the schematic
shown overleaf. Your numbers for these nodes may be different.ELE2504 – Electronic design and analysis 22
Transient Analysis plots of input and output ...
Note use of scope cursors to determine peak-to-peak voltage of output.
Circuit schematic showing node voltages (quiescent) post analysis ....
Note that the Transient Analysis plot and node voltages show whether biasing is
correct/optimal.ELE2504 – Electronic design and analysis 23
Frequency responses – (Bode plot)
Sample setup for AC Analysis ...
Sample plot of AC Analysis
Note use of scope cursors to determine the –3dB break point at approximately 22 Hz.ELE2504 – Electronic design and analysis 24
Test (Optional)
Note that the measurements taken here are not expected to be accurate since it is assumed
they will be done with a digital voltmeter only, and waveforms may not be sinusoidal. In
building the circuit you may use a BC547 in place of the 2N22222.
1. Connect your circuit and measure the d.c. voltages around the circuit. If they are not as
expected, find the cause and rectify it.
2. Connect the test oscillator (shown below) to the input. It should be producing an
approximately sinusoidal signal of about 100kHz frequency and you can add an attenuator
to produce a small size of say 0.2v p/p. Measure, using a DVM, the magnitude of the
voltage gain at 100kHz.
3. Bypass RE with a capacitance of 0.47μF and again measure the voltage gain. You will
need to reduce the size of the signal input in order to keep the output sinusoidal. Reduce
it to an estimated 20mV.
4. Remove the bypass capacitor. Estimate the input resistance (at 100kHz) by adding a 1kW
resistor (R) in series with the oscillator to monitor base a.c. current. Measure the a.c.
voltage across this resistor, v. The input current is then iin = v/R, and the input resistance
R
in of the amplifier is Rin = Vin/iin – R.
5. Repeat 3 and 4 with the 0.47μF capacitor bypassing RE.
Note:
If using 4093, parallel all 6 gates to
provide maximum output current
capability.
Test oscillator to act as a source for the amplifier.
Report
● Show all design calculations.
● Show full cct design with all component values.
● Provide either –
o MCap plots for AC analysis, transient analysis and schematic showing node voltages
and/or
o Test results from testing built circuit.
● Comparison of results (measured or simulated) with specifications, drawing inferences and
conclusions.ELE2504 – Electronic design and analysis 25
Design assignment B
Description Marks out of Wtg(%) Due date
Design assignment B 0 0 Week 10
This assignment does not have to be submitted for marking. However it may be the subject of
a question in the examination.
Part A: Switching regulator design exercise
Theoretical design
Note: This design is entirely theoretical. You will not be expected to assemble the circuit
and test it.
Collect information
Data on the TL497AI switching voltage regulator is provided from the Texas Instruments
1989 Linear circuits data book, volume 3, pages 2-135 to 2-141. From this data assemble the
following:
● a table showing
● allowable input voltage range
● allowable output voltage range
● V ref (typical)
● switching transistor maximum current
● diode maximum current
● A sketch of the power dissipation rating curve.
Data on ferrite cores suitable for construction of inductors is also provided.
Design
Using this data and the typical application data (use the basic configuration even if current
values fall slightly outside the specified range), design a regulator to meet the specifications
below. Include component ratings in your design and choose the inductor core, wire size and
number of turns. Your design should also include thermal considerations by estimating the
heat loss. If necessary, specify heat sink thermal resistance.ELE2504 – Electronic design and analysis 26
Specifications:
Type of regulator : Step down
Input voltage Vi : 24
Output voltage Vo : +5V
Output current Io : 300 mA
Maximum output ripple Vr : 50 mv
Ambient temperature Ta : 50 deg C
Report
Present a report containing the following:
● assembled data
● design calculations, including inductor core choice/details
● a circuit sketch using the same schematic layout as in the data, and showing all
component values including ratings.ELE2504 – Electronic design and analysis 27ELE2504-Electronic design and analysis 40
(Source: Texas Instruments 1989, Linear circuits data book, vol. 3, p. 2-136. Reproduced with permission
from Texas Instruments Ltd.)ELE2504 -Electronic design and analysis 45
(Somce:TexasInstruments1989,Linear circuitsdata book,vol. 3,p.2-140.Reproduced with permission
from Texas Instruments Ltd)ELE2504 -Electronic design and analysis 46
(Somce:TexasInstruments1989,Linear circuitsdata book,vol. 3,p.2-140.Reproduced with permission
from Texas Instruments Ltd)ELE2504 -Electronic design and analysis 47
(Source: Texas Instruments 1989, Linear circuits data book, vol. 3, p. 2-139. Reproduced with permission
from Texas Instruments Ltd.)
© University of Southern QueenslandELE2504 -Electronic design and analysis 48
(Somce:TexasInstruments1989,Linear circuitsdata book,vol. 3,p.2-140.Reproduced with permission
from Texas Instruments Ltd)ELE2504 -Electronic design and analysis 49
Propert es of core assemble i s at25°C (without adjusters)
Stock number
RM6 RM6 RMl RM10 RMIO
228-214 228-220 228-236 228-242 221-268
Inductancefactor ""'-
Tumsfactor a
(turns for 1mH)
Effect ve permeability JJ.
Temp.coeft.of "•
(+25 to50"C) ppmi"C
Adjuster range
Max.residualplus eddy current coreloss
Tengenttand,+,111:JOkllz
at lOOkHz
Recommended frequency range(kHz)
Energystoragecapabtkty (mJ) UJ.,.,
B ... mT
160 250 250 250 400
79.06 63.25 63.25 63.25 50.00
±1% ±1% ±1% ±1% ±1%
109.5 171.1 146.0 99.67 159.5
51min. SOmin 73min. 50min. SOmin.
t54max. 241max. 219max. 149max. 239max.
+20% +14% +15% +17% +20%
0.34 X 10' 0.53 X 10' 0.47 X 1()-0 0.32 X 10" 0.51 X 10'
0.58 X 10" 0.91 X 1(}-' 0.82x 10"' 0.60X 1(}-' 0.96 X 10
5.5 to800 3.5to700 3to650 2to650 1.2 to500
0.383 0.245 MOo 1.731 10 . 82
250 250 250 250 250
RM
DataLibrary
IssuedJuly 1985 5n4
RM seriesferritecores
Stock numbers228-214to 228-258
A range of 5 of the most popular pcb mounting
ferrite cores covering three sizes.Of square design
which 11llows moximum boord ut lisation, this
series enables transformers or inductors to be
constructed to meet exactcustomer requirements.
The core material is equivae l nt to the commonly
known grades:A13-0.3-N28.Eachcoreis
supplied
Inkitformandcon"slstsof the folloWing:onepairof
matched half cores,one single section bobbin with
Integralpins onan 0.1ingrid,onepairof retan i
ing clipswithearth spikes andonecore adjuster.
To determine the number of turns required for a
particularinductanceuse the followingformula:
No,turns= vi""
Where L =inductance innH (1 H).
For frequencies in excess of 30kHz,the use of
stranded wire is beneficial when maximum a is
Features
e 5 versions availableinthree popular sz i es
e PCBmounting
e Compactdesign
e Mountn i g pinshave 2.64mm (0.11n)spocing
• l . •
required.
(nH/tum3') ±2% :t2% :!:2% ±2% :t2%
Magneticpropertie$of c:ores
Effectivepath length
Effectivepatharea
Effective volume
symbol RM6
I, 26.9mm
A., 31.3mm'
V0 840mm'
RM7
29.6mm
40.3mm'
1100mm'
RM JO
41.7mm
83.2mm'
3470mm'
Maximumturnsacmmodatedonbobbin
wiredia.(mm} RM6 RM7 RMJO wiredia.(mmJ RM6 RM7 RM10
0.2 205 306 612 0.56 25 36 87
0.224 160 250 484 0.71 19 33 59
0.25 127 209 402 0.8 13 19 44
0.315 87 131 246 1.0 9 11 25
0.4 47 76 160 1.25 4 9 19
0.5 36 50 98 1.5 3 7 11
(Source: RS Components 1985, Data sheet no.5774,July. Reproduced with permission from
RS Components Pty Ltd.)
UNIVERSITY
!If SOUTHERN
QUEE,'!'.
©University of SouthernOJeenslandELE2504 – Electronic design and analysis 48
© University of Southern QueenslandELE2504 – Electronic design and analysis 48
© University of Southern Queensland
Part B: Logarithmic amplifier design exercise
Design
Given any of the following transistor arrays, find the collector current versus base-emitter
voltage characteristic of the transistors from the data sheet which follows. Typical figures are
acceptable. Note that it is logarithmic over two decades of current:
LM or CA 3045, 3046 or 3086.
All of these are similar electrically and are readily available from suppliers. All are in
14 pin DIL packages and contain five similar transistors.
Design a logarithmic amplifier of the two-transistor type described in the Study Book based
on this device and LM108 op. amps. whose characteristic is to approximate the relationship:
V
out = –5 log (2Vin/2Vref)
as closely as possible at room temperature, over a two decade range of Vin from 0.1V to 10V.
Arrange for V
out to always be > 0V. Data for the LM108 is attached. Use to +/– 15 volt
supplies.
Simulation
Using MICROCAP simulate your circuit (using LM108 and transistor 2N2222 in
MICROCAP) and plot Vout versus Vin. Do this at three different temperatures, 0, 30 and
60 degree C. (Try various values for the lower limit in MICROCAP (0.2 or above until it
works.)
Also simulate the simple logarithmic amplifier given in the notes with the same op. amp. and
transistor and R = 10k ohms. (Specify MICROCAP Vin range at 10, 0.2, 0.1 for rapid results.)
Note that its variation with temperature is much greater than that of the other circuit.
Test
Assemble the circuit. Spurious oscillation will probably occur causing incorrect operation
and will need to be suppressed with capacitors such as fairly large values (4.7 µF or more)
from the output to ground. Do not forget to use compensation capacitors on the 308
according to the data sheet. If necessary, extra large values may help stop oscillation.
Measure the characteristics of your amplifier using a digital multimeter over its allowed
range of input voltages at room temperature.
Note: If you do not succeed in getting this circuit to work, it may be because of spurious
oscillations which are very common. The use of an oscilloscope would help to
identify and thus avoid these oscillations. However if you do not have access to an
oscilloscope, try adding capacitance in other places or ring the lecturer for advice.ELE2504 – Electronic design and analysis 49
© University of Southern QueenslandELE2504 – Electronic design and analysis 50
© University of Southern Queensland
(Source: National Semiconductor 1982, Linear databook, vol. 2, p. 2-19. Reproduced with permission from
National Semiconductor.)ELE2504 – Electronic design and analysis 51
© University of Southern Queensland
(Source: National Semiconductor 1982, Linear databook, vol. 2, p. 2-20. Reproduced with permission from
National Semiconductor.)ELE2504 – Electronic design and analysis 52
© University of Southern Queensland
Assignment 2
Description Marks out of Wtg(%) Due date
Assignment 2 200 20 3 October 2016
Part A: Active filter design exercise (Part 1) (8%)
Design
Design a 3 pole high pass filter with a Butterworth response having a cut-off frequency of
160 kHz. The filter is to use the second order circuit arrangement given below, and first order
section with LM108 or equivalent op. amps.
Theory
From the theoretical pole positions, compute and plot the following:
● the magnitude and phase of the normalised frequency response
● the group delay (–dϕ/dω) as a function of frequency.
Note that this will be a normalised plot with a cut-off frequency of 1 rad/sec.
Hints: Plot ω over the range 0.01 to 10 and define i 1 , and remember that a 3-pole
1
low pass response is in the form H ()
(s a) (s b) (s c)
complex poles.
where a, b, c are theELE2504 -Electronic design and analysis 53
The use of MathCAD or a similar programme makes this simple, but do it manually if
necessary. Six or eight points on a plot should be enough.
Simulation
Using MICROCAP simulate your circuit and plot gain, phase and group delay versus
frequency over the range 1 Hz to 10 kHz. This will also tell you if your design is correct.
Build and test
Using an LM324, build your filter and test it by taking about 7 readings from 20 kHz to 2kHz
using an oscilloscope (if you have access to one) or multimeter. If you feel your multimeter
cannot take accurate AC voltage measurements at these frequencies, go to the course website
for an alternative.ELE2504 -Electronic design and analysis 54
Part B: Oscillator design exercise (8%)
Measure/simulate
Measure the voltage-controlled resistance characteristic of a 2N 5484 (sim: 2N 3822)
N-channel JFET, by the following procedure:
1. Set up the following circuit, noting that the gate voltage is of the opposite polarity to the
drain voltage. If you do not have access to both these voltages, it is easy to put a voltage
divider (say a pot of value several k ohms) across almost any voltage to supply the gate
because it is a low current input.
2.
● Set V
GS to 0V.
● Vary RD over a range and at a variety of points, record VDS and VR in a table.
● Set V
GS to –1V, –2V, –3V, –4V in turn and for each, repeat the procedure above.
(simulate: –0.5, –1, –1.5, –2, –2.5).
3. Convert the V
R value to ID, by dividing by the R value (120Ω).
4. Plot a series of curves, one for each value of VGS on ID versus VDS axes.
5. For each curve identify the linear region around the origin, and evaluate:
R
DS
V
DS
I
D
6. Finally plot RDS versus VGS.ELE2504 -Electronic design and analysis 55
Design
Design a Wein Bridge Oscillator using a 741 operational amplifier as the active element.
Amplitude stabilisation is to be achieved using the JFET as a voltage controlled resistance.
Follow the procedure given in the study modules.
The oscillator specifications are to be individualised as supplied on the StudyDesk:
Power supply voltage: ______
Frequency: ______
Amplitude: ______
Test/simulate
The following test may be performed using any equipment you have access to. Results from
a moving coil multimeter or a digital multimeter are satisfactory, but an oscilloscope is
desirable.
Check the correct operation of your oscillator by measuring operating voltages at significant
nodes. These will need to be compared with design values in your report. These should
include the following points: + terminal of op. amp, output of op. amp., voltage across C1,
voltage on gate.
NB: If you suspect the oscillator is operating but is clipping, replace R3 and R4 with a pot,
say 10 k. This will act as an amplitude control, and will allow you to reduce the
amplitude below clipping level.
Report
Submit a written report which should contain only the following:
● a sketch of the final circuit
● a comparison in a table of design and measured voltages, both a.c. and d.c. at significant
nodes
● include your plots of the JFET characteristics
● any comments you may wish to make.
UNIVERSITY
Ill:SOUTHERN
QUEE
© University of Southern QueenslandELE2504 – Electronic design and analysis 48
© University of Southern Queensland
(Source: Linear Technology , www.linear.com/docs/1704 , 31 July 2015)© University of Southern Queensland
ELE2504- Electronic design and analysis 46ELE2504 – Electronic design and analysis 51
© University of Southern Queensland
Part D: Electronic integrated circuits ICs (4%)
Select two ICs and submit a short report for each, covering the following details:
● what the IC is (name, type)
● explanation of the IC's features and how it works
● sample circuit application making use of its feature(s) with a circuit operation
explanation (include any relevant calculations).
IC list:
4052
LM 335
NE 567
4028
LM 3915
LM 723
4N 29
LM 331ELE2504 – Electronic design and analysis 52
© University of Southern Queensland