C1/2 Homework 1 EGCP 456: Introduction to Logic Design with Nanotechnology Due: Monday, September 19, 2016 at 11:59PM as a single PDF to TITANium Please show your work For each problem, list all references used or students consulted (see EGCP 456 Collaboration Policy on TITANium) Turn this homework in digitally through TITANium as a single PDF file. Feel free to either use a word processing system to create your PDF, or print this PDF out, write on the paper, and then scan or take a picture to create a PDF to turn into Total Score [ /140 pts] 1. [2 x 10 pts] Find the Req for the following 32 nm transistors, using Req data from the following table. Assume all transistors are minimum length (L = 2 λ = 32 nm). Table of equivalent resistance Req (W/L= 1) of NMOS and PMOS transistors in a fictitious 32 nm process (with L = Lmin) at different operating voltages. For larger devices, divide Req by W/L. V DD (V) 0.8 0.9 1.0 1.1 NMOS (kW) 5 3 2.5 2.4 PMOS (kW) 16 8 6 5 a. NMOS, W = 6 λ in series with an NMOS, W = 16 λ, Vdd = 0.9 V b. PMOS, W = 12 λ in parallel with a PMOS, W = 4 λ, Vdd = 1.1 V 2. [10 pts] All transistors in a 45 nm CMOS 4-input NOR gate are 6 λ wide and 2 λ long. Calculate the capacitance of a single input if Cox = 65 fF/nm2 and CO = 4 fF/nm. 3. [2 x 10 pts] Calculate the output (junction) capacitance for the following 32 nm CMOS gates. For an NMOS assume: C j = 26 fF/nm2 and Cjsw = 3 fF/nm, and for PMOS assume: C j = 23 fF/nm2 and Cjsw = 2.6 fF/nm. Use L D = 5 nm. Assume minimum length transistors, and no shared diffusion between transistors. a. Inverter: PMOS W = 6 λ, NMOS W = 4 λ b. 2-input NAND: PMOS W = 6 λ, NMOS W = 8 λ 4. [15+15 pts] A copper wire is formed into the shape shown below and has an R = 1.41667 x 10-4W/. Since techniques to calculate the resistance of a corner are complex, approximate the resistance by calculating a reasonable lower bound and upper bound resistance between points A and B. Explain your reasoning.2/2 5. [60 pts] For the static CMOS device shown below, assume the following: R eqN=20 kW (for WN/LN=1, and LN=Lmin) R eqP=30 kW (for WP/LP=1, and LP=Lmin) All NMOS transistors have the same WN All PMOS transistors have the same WP a. [15 pts] Assuming WN=195 nm, find WP to balance the worst-case equivalent resistances of the PUN and PDN, show all work and assumptions. b. [15 pts] Assuming WP=195 nm, find WN to balance the worst-case equivalent resistances of the PUN and PDN, show all work and assumptions. c. [10 pts] Assuming input F settles to its final value after all of the other inputs have settled, can it be switched with another input to improve performance while maintaining the same functionality? If so, which one? d. [20 pts] Assuming WP=260 nm and that E=F=G=1 at all times, find WN to balance the worst-case equivalent resistances of the PUN and PDN, show all work and assumptions.