Design a state machine that has TWO outputs – one of which indicates when the number of '1's detected is even and one which indicates when it is odd. Inputs – Clock, X Outputs - Y,ZDesign a state machine that counts up in binary from 0 to 15 when the control input is a '1' and in reverse sequence when the control input is a '0'. Inputs – Clock, Control Outputs – A,B,C,D (D is MSB) Design a state machine that creates a delay based on a defined number of clock cycles. The delay should be triggered by a signal ST becoming high and the end of the delay should be indicated by the output TS becoming high for one clock cycle – the circuit should then wait for the next ST signal. Inputs – Clock, ST Outputs - TS