TUTORIAL QUESTIONS - Using VHDL to model Boolean Circuits Question 1. Draw circuits that correspond to the following statements a. C <= A; D<=A; b. C <= A XNOR (NOT B); c. C<= A when D='1' else B; d. X <= A and not B or not C and D; e. X <= (A or B)and(C or not D); f. C <= A when D='1'else B when E ='0' else D; g. signal s: bit_vector(1 downto 0); signal a, b, c, d, e: bit; with s select e <= a when s="00", b when s="01", c when s="10", d when others; Question 2. If A changes at time 5ns, at what time do each of the following concurrent statements execute? a. C <= A; D <= A; b. C <= A after 5 ns; E <= C or A after 7 ns; Question 3. Draw a circuit and the signal waveform that corresponds to the code extract signal A: bit:='0'; A<=not A after 2 ns; Question 4. Write a statement to implement the exclusive OR of signals A and B without using the xor or xnor operators.TUTORIAL QUESTIONS - Using VHDL to model Boolean Circuits Question 5. a. Write an entity for a module MOD1 which has three single bit inputs a, b and c and two single bit outputs d and e. b. Write an architecture for MOD1 if d = a.b.c e = d' Question 6. Given the concurrent statements R <= A after 5ns; -- statement 1 S <= R after 10 ns; -- statement 2 If A changes at time 3ns a. at what time will be the statement 1 executed ? b. at what time will be R updated? c. at what time will be statement 2 executed? d. At what time will be S updated? Question 7. a. Declare a bit_vector A and write a statement that assigns it the value 10101011. b. Assign the value 1 to the most significant bit of a 32 bit bus A. First declare the bus. c. Declare a 3 bit bus B and connect to it three single bit signals b0, b1 and b2 (there are two ways doing it). d. Combine 5 single bit signals a,b,c,d and e into a five bit bus. Question 8. Given the concurrent statements F <= '0'; F<='1' after 2ns; draw the waveform for F. Question 9. Draw the schematic symbols and then implement in VHDL the following components a. 2:1 Quad Multiplexer (uses 4 bit data lines) b. 3:8 line Decoder c. Single bit Full Adder d. 4 wordsx4bits Read Only Memory (ROM) storing the values of four hexa-decimal digits representing the year 2016 e. An RS latch implemented as two nor gates. Provide a data flow and also a functional VHDL model.