1. Compare the main memory organization schemes of contiguous-memory allocation, pure segmentation, and pure paging with respect to the following issues (9 points) a. external fragmentation, b. internal fragmentation, c. ability to share code across processes 2. Describe contiguous vs noncontiguous memory allocation (3 points) 3. Describe the difference between logical and physical memory( 4 points) 4. Consider a paging system with the page table stored in memory. (6 points) a. If a memory reference takes 200 nanoseconds, how long does a paged memory reference take? b. If we add associative registers, and 75 percent of all page-table references are found in the associative registers, what is the effective memory reference time? (Assume that finding a page-table entry in the associative registers takes zero time, if the entry is there.) 5. Consider the following reference string: (12 points) a. How many page faults would this string produce under the FIFO page replacement strategy with three frames? 3 1 3 5 3 2 4 2 1 5 3 1 2 4 b. How many page faults would this string produce under the OPT replacement strategy with three frames? 3 1 3 5 3 2 4 2 1 5 3 1 2 4 c. How many page faults would this string produce under the LRU replacement strategy with three frames? 3 1 3 5 3 2 4 2 1 5 3 1 2 4 HW3 COP4610 2 6. What is the cause of thrashing? How does the system detect thrashing? Once it detects thrashing, what can the system do to eliminate this problem?(6 points) 7. Consider a demand paging virtual memory system with 24 bit virtual address space, page size is 8192 (8KB or 2^13) and the system has 8 MB of main memory. Assume access time for main memory is 100 ns. Assume the page table is single level and stored in memory. (20 points) a. When we split a logical address into page number and offset within the page, how many bits are used for the page number, and how many bits are used for the offset? b. Assuming page table entries are 4 bytes each and a single level page table is used, how many bytes are required to store a page table? c. If the OS reserves 1 MB (128 frames) of physical memory for kernel code, buffers, etc., how many physical frames are left for demand paging? d. If no TLB (cache) is used, how long does a paged memory reference take? e. Suppose we add a TLB to the system to speed up logical to physical address translation. With a TLB access time of 10 ns and a TLB hit ration of 0.9 what is the effective memory access time? Assume we do a main memory page table look up after a TLB miss, and that the desired pages are always in main memory. f. Suppose at some point in time our TLB contains the entries: Page # Frame # Valid? 5 17 V 10 6 V 15 15 V The user attempts to access the logical address 0000 0001 0100 1011 0011 0100. Is this a TLB miss? Briefly explain. g. What is the physical address?