1 KD6002 – Electronic System Design (2016-17) Extended Workshop Exercise – Successive Approximation Analogue-to-Digital Converter System Information  This extended laboratory exercise is worth 20% of the KD6002 module mark  The hand-in date for submission of your report, in MS-Word-2010 format, is Thursday the 13th of April via the eLearning portal. (Instructions to follow) Objectives  To gain an understanding of the Successive Approximation A-to-D Conversion Process  To capture and verify a Verilog-HDL description of a Successive Approximation A-to-D Convertor, along with a test-bench.  To construct and test an A-to-D Convertor System using a Xilinx Coolrunner® 2 CPLD Board, R-2R ladder network module and voltage comparator circuit.  To make use of a potentiometer to control the speed of a DC Motor via ADC developed above. Resources  Xilinx ISE® Programmable Logic Design Suite Version 14.7 (available in laboratories E204/206 and as a free download from https://www.xilinx.com/products/design-tools/isedesign-suite/ise-webpack.html ).  Digilent® Incorporated CoolRunner-II CPLD Starter Board. (technical information available at: http://store.digilentinc.com/coolrunner-ii-cpld-starter-board-limited-time/ )  PDF document ‘SuccessiveApproxADC_Workshop_KD6002.pdf’, available on eLearning at: KD6002 → Learning Materials → Course Material - Ian Elliott → Workshop.2 Introduction DAC COMP Vref - + Control Logic C B[7] B[6] B[5] B[0] Digital Ouput (N) ........ ........ Vin Analogue Comparator Vdac if(V(+) > V(-), 1, 0) SAR B Figure 1 – Block Diagram of a Successive Approximation ADC3 Successive Approximation SAR = 8'b10000000; B = 8'b00000000; B = B | SAR; Delay C == 1 ? SAR = SAR >> 1; true B = B ^ SAR; false SAR == 0 ? End false true Vin > Vdac Vin < Vdac Shift SAR right 1 bit position Allows DAC and Comparator to stabilise 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 SAR B Vdac = N * VLSB VLSB = Vref/256 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 2 – Flowchart of Successive Approximation Algorithm Task 1 – Understanding the Successive Approximation Algorithm Figures 1 and 2 show the block structure and algorithm for a SA-ADC, the latter in the form of a flowchart. For the 8-bit system shown, there are two key registers – Successive Approximation Registers (SAR) and result register (B). Given the initial values of SAR and B, shown on figure 2, complete the blank table given below, in order to show how the conversion process is executed in a step-by-step manner. With reference to figure 2: Vref = 3.3 Volts 𝐠= ∑7 𝐽0 𝑛𝑝 × 2𝐍 ‘^’ is the bit-wise Exclusive-OR operation ‘|’ is the bit-wise logical-OR operation ‘>>’ is the logical shift right operation4 Apart from the row labelled ‘initial’, each row shows the state of the system at the dotted line in figure 2, after the logical-OR operation is carried out on the B and SAR registers. The completed table is provided as a guide. step SAR B Vdac Vin C initial 10000000 00000000 0.0 2.7 1 1 10000000 10000000 1.65 2.7 1 2 01000000 11000000 2.475 2.7 1 3 00100000 11100000 2.8875 2.7 0 4 00010000 11010000 2.68125 2.7 1 5 00001000 11011000 2.784375 2.7 0 6 00000100 11010100 2.7328125 2.7 0 7 00000010 11010010 2.70703125 2.7 0 8 00000001 11010001 2.694140625 2.7 1 end 00000000 11010001 2.694140625 2.7 1 step SAR B Vdac Vin C initial 10000000 00000000 0.0 1.31 1 1 2 3 4 5 6 7 8 end [10 marks] Task 2 – Derivation of the R-2R Ladder Network Digital-to-Analogue Converter output voltage. Figure 4 on page 7 of the accompanying PDF document, ‘SuccessiveApproxADC_Workshop_KD6002.pdf’, shows the circuit diagram of an 8-bit R- 2R ladder network digital-to-analogue converter. Given the information provided below figure 4, derive from first principles the expression for the output voltage of the network ‘Vdac’ in terms of the logic-1 voltage (Vref = 3.3 Volts) and the decimal equivalent of the digital input ‘DATA[7:0]’. Make use of circuit sketches to clearly show how you have arrived at the final relationship. [15 marks] Task 3 – Relating to the Schematic Diagram of the CPLD Internal Logic Study the schematic diagrams given in Figures 5, 6 and 7, in the accompanying document and provide answers to the following questions:5 i. Calculate the frequency of the system clock (Clock) used by the system shown in figure 5. [2 marks] ii. Write down the names of those blocks in figure 5 that contain sequential logic. [4 marks] iii. Write down the names of those blocks in figure 5 that contain combinational logic. [4 marks] iv. Identify which module (block) acts as the central controlling element in the system of Figure 5. [4 marks] v. Explain the behaviour of the SAR module, shown in figure 6, when the following conditions apply: reset = 1’b0, shift = 1’b1 and the ‘Clk’ input is pulsed from 0 to 1 (assume the SAR register was previously initialised by temporarily asserting reset to logic-1). [5 marks] vi. Referring to figure 7, complete the following truth table for the ‘SC’ module: A B clear_bit S 8’b01000000 8’b11000000 1 _____________ 8’b00001000 8’b01100000 0 8’b00000100 8’b11000100 1 8’b00000010 8’b11011000 0 8’b00000001 8’b11000000 1 [5 marks] vii. Explain the purpose of the module named ‘SC_Pulsegen’ shown in figure 7 (and instantiated in figure 5). [5 marks] viii. Complete the Verilog-HDL source description of the ‘ADC_FSM’ module given in figures 8 and 9, based on the state diagram given in figure 8. Include a full listing of the module in your report. [12 marks] Task 4 – Simulation and Construction of the Analogue Comparator and Input Potentiometer Breadboard Figure 16a shows a LTSpice® (http://www.linear.com/designtools/software/#LTspice ) schematic drawing of the Analogue Comparator circuit shown in figure 16. The LTSpice circuit file is provided on the eLearning site. Download the file ‘Test_LT1011.asc’ from Blackboard and open it using LTSpice. Execute the LTSpice menu command ‘Simulate – Run’ to view the transient simulation results in the waveform window. Go to the waveform window and execute the command ‘Tools – Write plot to a .wmf file’ from the main menu. Insert the resulting image file into your report document and comment on the results. Note – if you don’t want to include all of the parameter steps in the results, right-click over the waveforms and execute ‘Select Steps’, select Step 5 to see just one set of waveforms. [10 marks] The physical layout of the analogue comparator is shown on the right hand side of figure 16. Assemble the circuit as shown using the components and link wires provided.6 Task 5 – Completion of the ‘PWM_control’ module The Pulse Width Modulation control module generates an output pulse having a markspace ratio that is determined by the 8-bit value output by the ADC. Figure 10 shows the typical waveforms output by this module. Given the information shown alongside figure 10 and the partial Verilog-HDL source listing, produce a complete module description for the ‘PWM_control’ block and include a listing in your report. [10 marks] Task 6 – Simulation of the complete system ‘ADC_SuccApprox_CPLD’ using the associated test-module. All of the Verilog-HDL source files, including the partially complete ones, are provided on the eLearning site at: KD6002 → Learning Materials → Course Material → Ian Elliott → Workshop Download and extract all of the source files from the above location and create a Xilinx ISE project targeting the XC2C256 CPLD device. Add all of the source files to the project, being careful to associate the sources with the appropriate processes (Simulation, Implementation and All). Once the project is created and open, double-click on the top-level design source, ‘ADC_SuccApprox_CPLD’ and locate the instance of the display counter (dispcntr). With reference to figures 11, 12 and 13 of the presentation, explain the function of the display counter module within the design and why it is necessary to set the parameter ‘N’ to the value of 2 for simulation, and 12 for implementation. [5 marks] Set the ‘dispcntr’ parameter, N = 2. With the design view set to simulation (behavioural), invoke the simulation of the top-level test-module. The simulation tool will open (ISim) and it will run for the default time of 1000 ns with the top-level waveforms added to the waveform window. In the main ISim window, go to the ‘Instance and Process name’ panel and select the ‘dut’. Write down a sentence to explain the effect this has on what is shown in the ‘Simulation Objects’ panel. [3 marks] In the ‘Simulation Objects’ panel, select all of the signals from ‘Reset’ down to ‘Clock’ and add them to the waveform window. Expand the ‘dut’ instance in the ‘Instance and Process name’ panel, and select the ‘ADC_FSM’ instance ‘FSM1’. Add the object named ‘state’ in the ‘Simulation Objects’ panel to the waveform window. Add the signals ‘ramp’ and ‘data_reg’, located inside the ‘PWM1’ instance, to the waveform window.7 Float the waveform window out from the main ISim window and restart the simulation. Execute ‘Simulation – Run All’ from the main ISim menu and zoom out to the full extent of the resulting waveforms. Set the radix of the 22-bit ‘analogue signals to unsigned decimal. Set the radix of any other bus signals to hexadecimal. The following list shows the required vertical ordering of the waveforms in the wave window /test_ADC_SuccApprox_CPLD/dut/Reset /test_ADC_SuccApprox_CPLD/RstB /test_ADC_SuccApprox_CPLD/CLK8M /test_ADC_SuccApprox_CPLD/dut/Clock /test_ADC_SuccApprox_CPLD/DataRead /test_ADC_SuccApprox_CPLD/Stop /test_ADC_SuccApprox_CPLD/Vin /test_ADC_SuccApprox_CPLD/Vdac /test_ADC_SuccApprox_CPLD/Comp /test_ADC_SuccApprox_CPLD/Busy /test_ADC_SuccApprox_CPLD/EOC /test_ADC_SuccApprox_CPLD/dut/StartConv /test_ADC_SuccApprox_CPLD/dut/SAR /test_ADC_SuccApprox_CPLD/dut/S /test_ADC_SuccApprox_CPLD/Data /test_ADC_SuccApprox_CPLD/dut/FSM1/state /test_ADC_SuccApprox_CPLD/dut/Shift_SAR /test_ADC_SuccApprox_CPLD/dut/Init_SAR /test_ADC_SuccApprox_CPLD/dut/SAR_LSB /test_ADC_SuccApprox_CPLD/dut/Clear_bit /test_ADC_SuccApprox_CPLD/dut/Load_DRES /test_ADC_SuccApprox_CPLD/dut/Clear_DRES /test_ADC_SuccApprox_CPLD/dut/hex_disp /test_ADC_SuccApprox_CPLD/dut/sel_disp /test_ADC_SuccApprox_CPLD/DIR /test_ADC_SuccApprox_CPLD/dut/PWM1/data_reg /test_ADC_SuccApprox_CPLD/dut/PWM1/ramp /test_ADC_SuccApprox_CPLD/PWM Capture an image of the entire view of the simulation waveforms and paste/crop into your report, adding an appropriate caption. Given the value of the analogue input ‘Vin’, comment on the output waveform ‘PWM’. [8 marks] Zoom into the waveforms to show the time range 200 ns to 300 ns, this should enclose a single analogue-to-digital conversion operation. Measure the time interval between the rising-edge of the ‘StartConv’ pulse and rising-edge of the ‘EOC’ pulse. Write down this value in your report and state it’s significance. Capture an image of the waveforms and paste/crop into your report with an appropriate caption. [10 marks] Zoom further into the waveforms to be able to see the 8MHz clock (CLK8M) and the divided clock (Clock). Measure the period of the ‘Clock’ waveform and capture a screen image.8 Calculate the frequency of the system clock signal, named ‘Clock’, and explain any discrepancy with the expected value. [6 marks] Measure the time interval between consecutive ‘StartConv’ pulses, hence calculate the number of conversions taking place every second. Given the CPLD clock is 8MHz, compare the above result with the theoretical value and comment. [4 marks] Measure the period of the pulse width modulation signal, PWM, and also the width of the logic-1 pulse. Use these to calculate the ‘mark-to-space’ ratio of the PWM output and comment on this result in terms of how it relates to the analogue input ‘Vin’. [5 marks] Open the Verilog source description for the test-module and change the analogue input to 2.25 Volts. Re-launch the simulation and re-run in order to produce a new set of results in the waveform window. Comment on the PWM output signal. [4 marks] Task 7 – Implementation and Testing of the System Before implementing the system it is necessary to set the parameter ‘N’ of the display counter (dispcntr) instance to 12. Figure 15 shows the contents of the ‘user constraint file’ (ucf) required as part of the implementation process. Create a file named ‘ADC_SuccApprox_CPLD.ucf’ and copy the text shown in the box alongside figure 15 into the file. Write a couple of sentences to explain the purpose of the above file, in the context of the implementation process. [4 marks] Change the design view in the Xilinx ISE Project Navigator to ‘Implementation’ and select the top-level design source. Now move the cursor into the ‘Processes’ pane below and invoke the ‘Implement Design’ process. (If any errors are reported and the implementation process fails, it will be necessary to investigate these and correct them before repeating the procedure). Expand the ‘Implement Design’ process within the Process pane so that the sub-processes (Synthesis, Translate …etc) can be seen. On successful completion of the implementation processes, capture a screen image of the following and paste into your report: i. A cropped image showing the processes window pane and the successful completion of the implementation sub-processes. ii. A cropped image showing the first page of the CPLD implementation report, including the resources summary table. Comment briefly on the statistics presented in the resources summary table. [10 marks] Connect up the hardware as per figure 15 in the accompanying handout (i.e. without the DC motor).9 Double-click on the ‘Configure Target Device’ process to launch the ‘iMPACT’ device programming tool. After initialising the programming cable and establishing communication with the CPLD board, associate the device with the JEDEC programming file, ‘ADC_SuccApprox_CPLD.jed’, and program the CPLD. Experiment with the various input/output devices (potentiometer, push-button, sliding switches, LEDs and 7-segment display) and make notes concerning the operation of the system. Relate your observations to the simulation results gained earlier. [10 marks] Figure 17 shows the hardware configuration with the DC motor connected. To test this setup, it will necessary to make changes to the user constraint file (*.ucf) and re-run the implementation processes prior to reprogramming the CPLD. Important: Observe the note next to figure 17 regarding connecting up the power supply to the DC motor (9 Volt battery). Repeat the testing carried out above and make notes concerning the behaviour of the DC motor in response the potentiometer located on the breadboard. [5 marks] [Total Marks = 160]  Ian Elliott 2-1-17