1 University of Essex School of Computer Science and Electronic Engineering Introduction to Computer Aided Design Multisim 8 A 'GETTING-STARTED'TUTORIAL for Digital Circuits Nikolaos Thomos (Note that this tutorial assumes the Analogue version has already been completed) CONTENTS 1.Half Adder 2. Full Adder 3. Synchronous Binary Counter Appendix Results log2 INTRODUCTION TO DIGITAL SIMULATION USING MULTISIM This digital introduction consists of three parts; Exercise 1 considers a half-adder formedfrom basic NAND gates, Exercise 2 uses the half-adder to construct a full-adder, and Exercise 3 considers a synchronous binary up-counter using J-K bistables. Note that circuits in this tutorial are using the ANSIconvention.3 Exercise 1: Half Adder MultiSIM provides both ideal (generic) and actual logic devices, where the latter model the real parameters of manufacturers' physical circuits. Click on the appropriate icons and examine the model data to see the differences (pay special attention to the propagation delay because this will be significant when designs are simulated). For the purposes of this tutorial, the 74LS series gates will be used to demonstrate the propagation delays as realistically as possible. The propagation delay, or gate delay, is the length of time, which starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change. The figure below illustrates propagation delays in a 3-bit asynchronous binary counter. We can notice that logic low -to- logic high transition of Q0 occurs a delay time tPLH after the positive going transition of the clock pulse. The logic low-tohigh transition of Q1 occurs one delay time tPLH after positive going transition of Q0. There are various ways to build a half-adder circuit but in this exercise we will design using NAND gates and inverters. The truth table for a half-adder is shown in Table 1. Table 1: Truth Table for half Adder Inputs Outputs B A Carry Sum 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 04 Schematic Capture Construct a half adder so that it looks like Figure 1. You will need four NAND gates, type 74LS00D (there are four in a package, identified as A, B, C and D during the 'place' process) and three inverters of type 74LS04D (six in a package). Add power supply (VCC) and ground (GND) connections. The bits to be summed are labelled VINA and VINB (you may use other names), with outputs SUM and CARRY. Save the circuit design once complete, as it will be needed in this form later. Figure 1: Half Adder circuit5 Adding Instruments When simulating digital circuits, or testing real ones, a logic analyser is the preferred 'viewing' tool, since it is potentially able to display simultaneously a large number of digital signals, unlike an ordinary oscilloscope. On the input side, a Word Generator is the usual signal source. Place instances of both from the 'Instruments' menu on the right of the screen. The wiring should be as shown below: the logic analyser is connected to monitor the inputs (channels* 1 and 2), all intermediate nodes in the circuit, and the outputs (channels 7 and 8). Note that the word generator will need to be flipped horizontally so bits 0 to 15 are on its right side!!! Figure 2. Half Adder with instruments * There appears to be an inconsistency in the labelling of the 16 inputs which looks like '1' to 'F'. The range should be 1 to 10 or 0 to F if using hexadecimal, or 1 to 16 if decimal.6 Setting-up the instruments Word Generator Double click the word generator icon in the circuit layout to open its setup display, which shouldbe like Figure 3; it can generate any sequence of bit patterns, 32 bits at a time. Set Display initially to Dec (decimal) and enter the values 0 to 3 on the right (the illustration in Fig.3 shows the Binary mode). Set the Start and Stop positions by right clicking on the appropriate rows. Set Cursor to the first row (this will need to be reset after each trial.) Set Trigger to Internal and Frequency initially to 1 kHz; this is the rate at which output bit patterns will be generated. Figure 3. Word generator setup7 Logic Analyser Open the logic analyser window and click Set to open the Clock Setup sub-screen. Set Clock Source to Internal and clock rate 10 kHz. Click Accept. Since the Word Generator has been set to 1 kHz, this means that the analyser will show 10 samples of the logic outputs for each state of the inputs. (Using a higher ratio of output/input frequencies will allow more accurate estimates of factors like propagation delay.) In the main window, set Clocks/Div initially to 1; you will later need to increase this number to 'widen' the view of the circuit outputs so that the full input sequence can be seen (this is the same process as reducing the time base speed on an oscilloscope). Figure 4. Logic Analyser setup screensRunning the simulation In the Controls box of the Word generator screen, make sure you have set Start and End positions for the output sequence, and set the Cursor to the first output. Click Burst. The Logic Analyser display should be like Figure 5. Note that, the Clocks/Div setting is 4. Before doing a repeat run of a simulation, ensure that the main Multisim On/Off switch is set to OFF, set the Word Generator cursor to the first output and Reset the LogicAnalyser. Figure 5. Half Adder Logic Analyseroutput Experiment with the Word Generator and Analyser clock values (try 1 MHz/10 MHz and 10 MHz/100 MHz) and explain what happens to the output waveforms. Figure 6 shows the result for the 1/10 MHz case. Note that the maximum clock rate is 100 MHz, which means samples are taken at 10 ns intervals; for obvious reasons the analyser sample rate should be at least twice the clock rate on the Word Generator side. When operating at maximum frequency, measure the worst-case propagation delay using the T1 and T2 cursors (immediately above the waveform display). This should be the delay between a transition at one of the inputs and a change that it produces at either or both of the outputs.78 Figure 6. Half adder running at 1 MHz with 10 MHz analyser clockrate.9 Exercise 2. Full Adder Figure 7 shows the Truth Table of a Full Adder: this has an additional input, Cin, that enables the circuit to be cascadedwith others to perform binary addition on words of any length (but there is an upper limit that depends on operating frequency and the side effects of cumulative propagation delays). The inputs are, in fact, interchangeable: all we really need is a circuit that outputs a two bit number in the range 0 to 3 that represents the number of 1s on the three inputs. However, here we adopt a hierarchical approach which means the Full Adder will be made from two half adder building blocks: one that computes the sum of A and B, while the second deals with the external Carry input. Inputs Outputs B A Cin Carry Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Figure 7. Truth Table for Full Adder Create a half adder sub-circuit as follows: 1. Open the original 'bare' half adder circuit (i.e. without instruments). 2. Remove the voltage source (VCC) and digital ground (GND) 3. Select all components of the half adder and copy to the clipboard 4. Select File – New to open a new editing screen 5. Within the new screen, Right Click – Paste as Subcircuit. This opens a SubcircuitName window. Enter half_adder – OK. 6. A skeleton form will appear which can be placed in the new screen. 7. Repeat steps 5 and 6 to place a second half_adder symbol.10 Full Adder wiring and instrumentation Construct the Full Adder as shown in Figure 8. As well as the two half adder subunits, you will need one OR gate from the four available in a 74LS32 device. Confirm by truth tables for the individual half adders that this arrangement correctly generates the overall Carry Out signal. Add instruments as shown, and program the Word Generator to output the necessary eight possible input combinations in the sequence 000 – 111 (0 - 7). Figure 8. Full adder with instruments Figure 9. Full adder Word Generator setup screen11 Full Adder testing After running a full sequence through the completed Full Adder as previously the output should resemble Figure 11. Note that the Clocks/Div setting has been increased to 8 to accommodate all of the sequence on the display. You should then repeat the process with 1 MHz then 10 MHz rates set on the Word Generator, using 10 MHz and 100 MHz respectively on the Analyser. The effects of propagation delays should become very apparent. Examine the detailed parameters of the TTL devices used and estimate from the circuits what the worst-case delay from any input transition to the outputshould be. Figure 11 Full Adder logic analyser screen Alternative Implementation If there is time construct a version of the Full Adder using a decoder and OR functions: you will need one 74LS138 3 to 8 decoder and two four-input NAND gates (why not OR gates here?). Compare its propagation delay performance with that of the hierarchical version above.12 Exercise 3 Synchronous 3-bit binary counter Capture and instrument the circuit in Figure 12. You will need three 74LS73 J-K flip-flops and one 74LS08 two-input AND gate. By this stage you should be able to do it without detailed instructions. You will need to activate the circuit using the on/off rocker switch at top left of the main screen. Let it run for a few seconds, then examine the output in detail by manipulating the slider on the analyser display. Measure the period of the most significant bit output. You could alternatively use the word generator in 'Burst' mode as previously to produce the clock, in which case one bit of its output could be used to reset the counter at the start of a sequence: note that the clear (CLR) inputs on the flip flops are active LOW. Figure 13 shows typical results for 1 kHz and 10 MHz clock rates. If there is time, examine the timing behaviour of the asychronous version of this circuit. Figure 12. 3 bit binary synchronous counter13 Figure 13 Synchronous counter outputs for 1 kHz clock rate 10 MHz 10 MHz zoomed, with cursors being used for measurement of propagation delay14 Appendix Modifying Component Parameters There may be times when you want to change the parameters of a component (for example changing the current gain of a transistor or the propagation delay of a logic gate). This can be carried out by editing the simulation model of a component that has been placed on a schematic. To illustrate this process, an example is given below of changing the delay of a NAND gate. • place a 74LS00D 2-input NAND gate • place the cursor over top of the component, double left click – Edit Model • change the propagation delays from 15 ns to 50n • click Change Part Model – OK you will notice an asterisk appears by the component name to indicate that one of the model parameters has changed and it is no longer a standard component from the multiSIM library. try the procedure again by placing a copy of the new component on the editing screen andthen modify this version.You should find the latest component has a double asterisk. This indicates that this version of the component is different yet again. Note that this process creates local instances of the components, it does not modify thestandard multiSIM library15