ECE4133: Instrumentation Design Course instructor: D. F. Lovely ([email protected]) Last update: 18th December, 2016 WEB Via Desire2Learn course management system LABORATORY #3: Single op-amp differential amplifier If you are not familiar with the PSpice circuit simulation software, it is highly recommended that you go through the tutorial that is on the course WEB site. For those who have had some PSpice experience, the documents "PSpice Basics" and "PSpice - More details" provide a brief refresher. Objective: The goals of this laboratory are to investigate the limitations of a differential amplifier implemented using a single op-amp. In particular, the effect of resistor tolerance on the common-mode rejection ratio (CMRR) will be highlighted. This will entail using PSpice to vary the tolerance of a component and to perform a worst case analysis. There are twelve Tasks associated with this laboratory and four short Questions (Total possible marks: 70)Laboratory #3 Single op-amp differential amplifier 2/8 ECE4133: Instrumentation Design DFL, 2002, 2016 Objective: The goal of this laboratory is to investigate the limitations of a simple differential amplifier that employs a single op-amp. This will include an investigation into both the differential gain, Ad, and the common-mode gain, ACM, performance of the differential amplifier with regard to resistor mis-matching. The overall laboratory involves two distinct phases: a) Hand calculations based on theory. b) Verification via computer simulation (PSpice). Performance goals: The differential amplifier used in this study will employ the Texas Instruments TL081 JFET operational amplifier1 (see data sheet: TL081.pdf) operating from a bipolar 15V supply. The performance goals for the required differential amplifier are as follows: Table L3.1: Amplifier specifications In addition, the amplifier should provide enough output current drive to feed a 1k load resistance. 1 Although this device is now close to being obsolete having been first introduced in by Texas Instruments in 1977, this does not detract from the knowledge to be gained from this laboratory. Parameter Symbol Value Units Differential gain AD 100 V/V Differential input resistance Rid 2 kΩ Upper bandwidth f(-3dB) 1 kHz CMRR (@100Hz) 80 dBLaboratory #3 Single op-amp differential amplifier 3/8 ECE4133: Instrumentation Design DFL, 2002, 2016 PART A: Design by hand calculations/theory A simple differential amplifier based upon a single op-amp is shown below in Figure L3.1. This circuit was described and discussed in Lecture 13. Figure L3.1: Simple differential amplifier using one op amp Design Task #1: (3 marks) Based upon the specifications laid out in Table L3.1, choose the appropriate nominal values of resistors R1, R2, R3 and R4. Design Task #2: (2 marks) Using the device data sheet for the TL081 op-amp, estimate the -3dB bandwidth of this amplifier. Does this meet the required specifications? The common-mode rejection ratio (CMRR) of this circuit is heavily influenced by the resistor matching. For zero common-mode gain, ACM, it is necessary that: 3 4 1 2 R R R R  If this condition is not met, then the ACM is non-zero, and the CMRR is finite Design Task #3: (5 marks) Show that if the resistors are not matched, then the common-mode gain, ACM, can be approximated by: 1 4 2 3 CM 1 3 4 R R R R A R (R R )   Laboratory #3 Single op-amp differential amplifier 4/8 ECE4133: Instrumentation Design DFL, 2002, 2016 In a real design scenario, it is impossible to match these resistors perfectly, so an estimate of the worst case common-mode gain, ACM, needs to be made. Design Task #4: (5 marks) Determine the worst case common-mode gain, ACM, for the situation of 5% and 1% tolerance resistors. Consider the worst case to be that when R1 and R4 are at the high end of their range, while at the same time R2 and R3 are at the low end. Express the common-mode gain in dB. Does 1% or 5% tolerance resistors meet the required CMRR specification? PART B: Simulation using PSpice Set up a project in PSpice to simulate this circuit. Replace any existing title block with the ECE4133 version obtained from the associated ECE4133.olb library (D2L: Laboratory exercise – Resources – PSpice libraries). The title block should be placed in the lower right-hand corner of schematic sheet so that the borders of the sheet and the border of the title block coincide. Add an appropriate title and include your name in the title block. Use the TL081 macro model that is included in this library for the operational amplifier. Initial investigation into the design performance Question/Task #5: (4 marks) Enter the schematic of the differential amplifier in PSpice under SCHEMATIC1. Add power connections for a bipolar 15V supply. Drive the circuit differentially from an ideal sinusoidal voltage source and feed the output of the amplifier into a 1k load. Create the netlist and ensure that there are no errors. Place a copy of the netlist in a text box on the schematic and print. Create a simulation profile for this schematic, called "Diff gain", to conduct an AC Sweep analysis of the circuit. Sweep the AC source from a frequency of 1Hz to 1MHz with a resolution of 100 points per decade. Question/Task #6: (4 marks) Run the simulation and display the Bode magnitude response (Ad) of the amplifier to a differential input. Using the cursor features of Probe, measure the differential gain at 100Hz and determine the -3dB bandwidth. Annotate the Bode plot with this information and include in your report. Compare the different gain to that of the specifications givenLaboratory #3 Single op-amp differential amplifier 5/8 ECE4133: Instrumentation Design DFL, 2002, 2016 in Table L1.1. Also compare the simulated bandwidth with that determined in Design Task #2. Question/Task #7: (4 marks) Add a second schematic page to the design – SCHEMATIC2. Copy the original schematic to this page and modify it to enable the common-mode gain to be simulated. Print out the schematic, annotated with the netlist and include it in your report. Create a simulation profile, called "CM gain", to conduct an investigation into the common-mode response of the amplifier. As before, sweep the AC source from a frequency of 1Hz to 1MHz with a resolution of 100 points per decade. Run the simulation and display the Bode magnitude response (ACM) of the amplifier to a common-mode signal. Question/Task #8: (3 marks) Using the cursor function, measure the value of the common-mode gain, ACM, at a frequency of 100Hz. Annotate the Bode magnitude response with the measured common-mode gain and print out the graph. Using the results of Question/Task #5, determine the CMRR of the amplifier at 100 Hz. Does this meet the design specification? Evaluating the effect of component tolerance To evaluate the effect of resistor mismatch, PSpice can be used to assign a device tolerance to a component. To do this it is necessary to modify the properties of the component. In this laboratory, an investigation is to be made regarding the effect of resistor tolerance on the value of differential and common-mode gains. If you are not sure about this procedure, complete details is given in application note "AN#2 - Modeling component tolerances" that can be found in the Laboratory - Resource section of the course WEB site. Assign a tolerance of 5% to resistors R1, R2, R3 and R4. These resistors should now include an extra notation on the schematic giving the tolerance. Don't forget to include the percentage sign with the "5"! To perform a tolerance evaluation, a slightly different simulation profile needs to be created. With PSpice there are two different ways in which this can be performed. a) Monte Carlo analysis performs several simulations in which the component tolerances are varied randomly. This produces multiple data sets that can be plotted on the transient graph to show the variation. This type of analysis can take considerable time.Laboratory #3 Single op-amp differential amplifier 6/8 ECE4133: Instrumentation Design DFL, 2002, 2016 b) Worst case analysis performs a sensitivity analysis based upon a particular circuit parameter using a component value that is bounded by the tolerance specification. As this does not produce multiple simulation runs, the simulation time is shorter than that of a Monte Carlo analysis. In this laboratory, a worst case analysis is to be performed on the differential amplifier to ascertain how the common-mode gain is affected by the resistor tolerance. Create a new simulation profile and call it "CM gain WC". Set up the analysis type as before, AC Sweep, with the same parameters. This is readily achieved by deriving the new profile from the existing one. Add a MonteCarlo/Worst Case analysis: Dialog: Simulation Settings – Worst Case Minimum Check the Worst Case option Enter V(U1:OUT) for the output variable Select 'only DEV' in the Worst Case / Sensitivity options Set Limit devices to type 'R' Click on 'more settings' Ensure that 'Greatest distance from the nominal run (YMAX) select' is the Find variable Select Worst Case direction – HI …OK This causes the worst case analysis to vary only the resistors based on a device tolerance (there is also a lot tolerance – see manual) to find the highest value of the output voltage. This will correspond to the highest common-mode gain. Run the simulation, select all data sets and display the common-mode gain as before. The resultant graph should resemble Figure L3.2. Figure L3.2: Worst case analysis for 5% resistor toleranceLaboratory #3 Single op-amp differential amplifier 7/8 ECE4133: Instrumentation Design DFL, 2002, 2016 On this graph, the bottom trace is termed the nominal run. That is the value of the common-mode gain when the resistors are exact, ie. no tolerance variation. This should be the same as the previous simulation, prior to the adding of a tolerance value. The top trace is the worst case common-mode gain, with resistor tolerance taken into account. Question/Task #9: (6 marks) Annotate the plot with the values of the common-mode gain, ACM, at 100Hz for both the nominal and worst case plots for the 5% resistor case. Edit the schematic, change the resistor tolerance to 1%, and repeat the simulation. Note and record the new values of the worst case common-mode gain. Compare this to the theoretical worst case figures derived in Design Task #4. To determine whether this design meets the specification shown in Table L3.1 we need to calculate the common-mode rejection ratio (CMRR). To do this we need to know both the common-mode and differential gains. We have now seen how resistor tolerance affects the common-mode gain, but no investigation into how resistor tolerance affects the differential gain has been made. Question/Task #10: (6 marks) Switch back to SCHEMATIC1. Add a tolerance specification to resistors, R1, R2, R3 & R4 of 1%. Simulate twice using a worst case analysis, once in each direction, and display the results in the form of two Bode magnitude plots of the differential gain, Ad. Annotate the plots to show the maximum and minimum values of differential gain at 100 Hz and include in your report. Comment on this variation from the nominal designed value of 40 dB. Question/Task #11: (10 marks) Switch back to SCHEMATIC2. Repeat the common-mode gain simulations of Question/Task #9 for resistor tolerances of 2%, 0.5%, 0.1%, 0.05% and 0.01%. Tabulate the worst case common-mode gain, ACM, at 100 Hz against the resistor tolerance. Using Excel or some other 3rd party software, plot the worst case commonmode gain in dB against the resistor tolerance. Use a logarithmic scale for the resistor tolerance. Identify two specific regions of this graph and give an explanation. Question/Task #12: (3 marks) From the measurements and graph produced in Question/Task #11, estimate the required resistor matching necessary for a common-mode rejection ratio of 80 dB. Find a supplier of such a resistor.Laboratory #3 Single op-amp differential amplifier 8/8 ECE4133: Instrumentation Design DFL, 2002, 2016 Additional Questions: 1. Assume the resistors employed in this amplifier have a tolerance of 0.1% (E192). In addition, the temperature coefficient, , of these resistors is 50 ppm/C. What is the maximum allowable temperature variation, T, between resistors that will maintain the matching requirement necessary to meet the CMRR specification of 80dB? (6 marks) 2. If the resistor matching was perfect, what factor ultimately limits the CMRR of the amplifier? Do the results, which were obtained during the course of this laboratory, support your conclusions? (2 marks) 3. Resistors with a tolerance of 1% are often referred to as E96 series, while those with a 5% tolerance as E24 series. What does this mean? (1 mark) 4. If this circuit was to be used in a practical situation, what other factor, other than temperature, will affect the will affect the performance of this differential amplifier? (1 mark) Conclusions: (5 marks) Summarize the findings of this laboratory with regard to the limitations of the single opamp differential amplifier. State what you have learnt in performing this exercise. What skills have you acquired with PSpice?