Realization of Memory-tester based on FSM using Verilog and CPLD or FPGA. Create a memory tester using Verilog. Conduct some test by writing values and reading it from memory to detect faults in memory chips. Different tests are : 1) Write 55 hex (0101 0101) and read it 2) AA hexadecimal (1010 1010) and read it. (55 & AA is to test adjacent locks in memory) 3) Walking ones test. Functional Block diagram Need to produce verilog code for each module. Here the tristate buffer module could be in the RAM itself as inout wire. State diagram for the FSM can be as follows FSM state diagram : I can provide the basic verilog codes for all the modules. Errors may be there in the verilog codes, identify it and correct it. Requirement : 1. Explain the function of the codes in each module briefly for me to learn, 2. Individual modules are to be tested first, so write the test benches for each of the module and produce a simulation for each of it. Scribe notes on it just for my understanding along with screenshots. 3. After each module is tested , put all the modules together and do module instantiations connecting one module to other and write the test bench to test it. 4. To test it, write 55 in the memory locations in complete , the read it out. Next do AA and then walking ones as well. Then make one test extra say 55h and try to make a mistake knowingly and let the FSM receives ~fab from the Comparator module and shows error in FSM. Simulations are to be there in each test. 5. Then explain me briefly how it will be synthesised and implemented in to a CPLD coolrunner 2. 6. Need a screen recording of the above things for the personal use explaining all those as well. **********************************************