ASIC Design - ELEC 30003 - Spring - 1 7 - CW 2 - R - QP ELEC 30003 Page 1 o f 5 Group Assignment – Spring 2017 ASIC Design (ELEC 30003) Submission Date: 3 rd May , 2017 Total Marks: 100 Introduction This is a group assignment aimed to give the student s exposure to apply the VHDL language for the simulation and synthesis of digita l systems . This also provides an opportunity for the students to design and implement digital system using contemporary VHDL design tools . For this assessment , the students will be grouped in g roup size of two or three students and the group will carry ou t all various tasks of this assessment. Students will be given ten weeks to accomplis h various tasks. Students will follow up on a regular basis and feedback will be provided to them on their work during the execution of the task s . Each group will demonst rate their work in the week 14 of the semester. O riginality and understanding of the work is justified through Q & A during the presentation followed by demonstration and will last for 20 to 25 minutes for each group . Outcomes of the assignment 1. Design, i mplement digital hardware/system on CPLD/FPGA target board and report with the help of literature review working in groups; and 2. Present interactively and argue the audience questions communicating them the analysed data related to the designed system. Ass ignment tasks Model a medium scale digital component using VHDL , create a test bench to apply various stimulus to it, and demonstrate its functionality for various test cases through simulated waveform and configuration on the DE2 - 115 target board . The pr ecise component to be modeled will be allocated on group basis. The device allocations will be provided in a separate list on Moodle along with a data sheet defining the operation of each device. ASIC Design - ELEC 30003 - Spring - 1 7 - CW 2 - R - QP ELEC 30003 Page 2 o f 5 You may use any VHDL simulation tool to complete the assign ment but it is recommended to use Altera Quartus II web edition as installed in computer rooms. This package i s available for free download from www.altera.com – registration and license agreement required. You should submit your work electronically to the ELEC30003 Moodle site as a single pdf document before 23:59 on the day of the deadline. Do not leave submission to the last minute. The file name for your submission should be your student identification number with t he extension .pdf. You should use this briefing document as a template. Fill your name and student ID at the start. Add your work in the sections below. Refer the evaluation grid sheet mentioning marking criteria for different tasks. Task 1 You are require d to insert here the pin diagram and brief description of all the pins of a medium scale digital component assigned to you. As a part of work proposal, you should clearly explain features and functionality of all pins except V CC and GND. No additional expl anation other than pin details are required. Pin details and operation of the digital component need to be discussed in the beginning during the demonstration of the assignment. ( 1 0 Marks) Task 2 You are required to produce and insert here the VHDL code of a medium scale digital component covering all its features . It should be well commented in consistent with the associated code . No additional commentary other than comments in the code will be ma rked. Include evidence, co pied from the VHDL design tool that the code compiles successfully without errors. You should show well understanding of the code during presentation of the work. ( 30 Marks) Task 3 You ar e required to produce and insert here the test bench in VHDL applying all possible stimuli to the modeled device . It should be well commented in consistent with the associated code for all different test cases . No additional commentary other than comments in the code will be marked. Include evidence, co pied from the VHDL design tool that the test bench compiles successfully without errors. You should show decent understanding of the code during presentation of the work. ( 2 0 Marks) Task 4 You are required to insert here a waveform covering all the features of functional model from the VHDL design tool to illustra te that the model works correctly for all test cases . Annotate comments on the waveform to explain all features for different test cases . Annotation should be consistent with simulation results. If you just supply a waveform without annotations marks will be deducted. Conciseness is important and ideally you will show your simulation on a single A4 page (landscape format suggested). Simulations longer than 3 A4 pages will not be marked. No commentary other