Evaluation Criteria for Mini Project:
Deliverables Aspects 0-2 3-4 5-6 7-8 9-10 Marks
Task-1 Details of
Digital
component
No description or
irrelevant description
of features and pin
details
Completely
inconsistent with
datasheet
Very poor
understanding of the
features and
functionality of pins
Describing minimal
features and pin
details
Mostly inconsistent
with the datasheet
Poor understanding
of the features and
functionality of pins
Describing few
features and pin
details
Marginally consistent
with the datasheet
Average
understanding of the
features and
functionality of pins
Describing most
features and pin
details
Completely
consistent with the
datasheet
Reasonably good
understanding of the
features and
functionality of pins
Describing all
features and pin
details
completely
consistent with the
datasheet
Very good
understanding of the
features and
functionality of pins
Deliverables Aspects 0-6 7-12 13-18 19-24 25-30 Marks
Task-2 VHDL
Program
and
compilation
report
Non-functional code,
not attempted,
meeting no
significant design
specifications
Cover no features or
irrelevant features
No comments or
completely
inconsistent
comments with the
associated code
Significant number of
spelling errors
Compilation report
with significant
amount of errors
Very poor
understanding of the
program
Completely
plagiarized code
Minimal functional
code as significant
portions of the code
is missing or
incomplete
Cover very few
features
Minimal comments
or mostly
inconsistent
comments with the
associated code
Large number of
spelling errors
Compilation report
with many errors
Poor understanding
of the program
Mostly plagiarized
code
Marginally functional
code with numerous
error
Cover few features
Marginally consistent
comments with the
associated code
Limited number of
spelling errors
Compilation report
with few errors
Average
understanding of the
program
Fairly original code
Mostly functional
code
Cover most features
Reasonably
consistent comments
with the associated
code
Few spelling errors
Compilation report
without errors
Reasonably well
understanding of the
code
Mostly original code
Completely
functional code
Cover all features
Completely
consistent comments
with the associated
code
No spelling mistakes
Compilation report
without errors
Very good
understanding of the
code
Completely original
code
Deliverables Aspects 0-4 5-8 9-12 13-16 17-20 Marks
Task-3 VHDL
Program of
the test
bench for
validation of
Non-functional code,
not attempted,
meeting no
significant design
specifications
Minimal functional
code as significant
portions of the code
is missing or
incomplete
Marginally functional
code with numerous
error
Cover few test cases
Mostly functional
code
Cover most test
cases
Completely
functional code
Cover all test cases
Completely
consistent commentsdigital
system and
compilation
report
Cover no test cases
or irrelevant test
cases
No comments or
completely
inconsistent
comments with the
associated code
Significant number of
spelling errors
Compilation report
with significant
amount of errors
Very poor
understanding of the
program
Completely
plagiarized code
Cover very few test
cases
Minimal comments
or inconsistent
comments with the
associated code
Large number of
spelling errors
Compilation report
with many errors
Poor understanding
of the program
Mostly plagiarized
code
Marginally consistent
comments with the
associated code
Limited number of
spelling errors
Compilation report
with few errors
Average
understanding of the
program
Fairly original code
Reasonably
consistent comments
with the associated
code
Few spelling errors
Compilation report
without errors
Reasonably well
understanding of the
code
Mostly original code
with the associated
code
No spelling mistakes
Compilation report
without errors
Very good
understanding of the
code
Completely original
code
Deliverables Aspects 0-4 5-8 9-12 13-16 17-20 Marks
Task-4 System
simulation
results with
annotation
No simulation results
or incorrect
simulation results for
all test cases
Cover no features or
irrelevant features
No annotation or
completely
inconsistent
annotation with
results
Largely incorrect
simulation results for
most test cases.
Cover very few
features
Inconsistent
annotation with
simulation results
Correct simulation
results for few test
cases
Cover few features
Marginally consistent
annotation with
simulation results
Correct simulation
results for most test
cases
Cover most features
Reasonable well
consistent annotation
with simulation
results
Correct simulation
results for all test
cases
Cover all features
Completely
consistent annotation
with simulation
results
Deliverables Aspects 0-4 5-8 9-12 13-16 17-20 Marks
Task-5 Demonstrati
on of results
with
explanation
Non-functional or
incorrect functional
results
Cover irrelevant
features while
demonstration
No explanation or
completely
inconsistent and/or
incorrect explanation
of results on the
target board
Incorrect functional
results for most test
cases
Cover very few
features while
demonstration
Mostly inconsistent
and/or incorrect
explanation of results
on the target board
Correct functional
results for few test
cases
Cover few features
while demonstration
Marginally consistent
and/or correct
explanation of results
on the target board
Correct functional
results for most test
cases
Cover most features
while demonstration
Reasonably well
consistent and/or
correct explanation
of results on the
target board
Correct functional
results for all test
cases
Cover all features
while demonstration
Completely
consistent and/or
correct explanation
of results on the
target board