ASIC Design-ELEC 30003-Spring-17-CW2-R-QP ELEC 30003 Page 1 of 5 Group Assignment – Spring 2017 ASIC Design (ELEC 30003) Submission Date: 3rd May, 2017 Total Marks: 100 Introduction This is a group assignment aimed to give the students exposure to apply the VHDL language for the simulation and synthesis of digital systems. This also provides an opportunity for the students to design and implement digital system using contemporary VHDL design tools. For this assessment, the students will be grouped in group size of two or three students and the group will carry out all various tasks of this assessment. Students will be given ten weeks to accomplish various tasks. Students will follow up on a regular basis and feedback will be provided to them on their work during the execution of the tasks. Each group will demonstrate their work in the week 14 of the semester. Originality and understanding of the work is justified through Q & A during the presentation followed by demonstration and will last for 20 to 25 minutes for each group. Outcomes of the assignment 1. Design, implement digital hardware/system on CPLD/FPGA target board and report with the help of literature review working in groups; and 2. Present interactively and argue the audience questions communicating them the analysed data related to the designed system. Assignment tasks Model a medium scale digital component using VHDL, create a test bench to apply various stimulus to it, and demonstrate its functionality for various test cases through simulated waveform and configuration on the DE2-115 target board. The precise component to be modeled will be allocated on group basis. The device allocations will be provided in a separate list on Moodle along with a data sheet defining the operation of each device.ASIC Design-ELEC 30003-Spring-17-CW2-R-QP ELEC 30003 Page 2 of 5 You may use any VHDL simulation tool to complete the assignment but it is recommended to use Altera Quartus II web edition as installed in computer rooms. This package is available for free download from www.altera.com – registration and license agreement required. You should submit your work electronically to the ELEC30003 Moodle site as a single pdf document before 23:59 on the day of the deadline. Do not leave submission to the last minute. The file name for your submission should be your student identification number with the extension .pdf. You should use this briefing document as a template. Fill your name and student ID at the start. Add your work in the sections below. Refer the evaluation grid sheet mentioning marking criteria for different tasks. Task 1 You are required to insert here the pin diagram and brief description of all the pins of a medium scale digital component assigned to you. As a part of work proposal, you should clearly explain features and functionality of all pins except VCC and GND. No additional explanation other than pin details are required. Pin details and operation of the digital component need to be discussed in the beginning during the demonstration of the assignment. (10 Marks) Task 2 You are required to produce and insert here the VHDL code of a medium scale digital component covering all its features. It should be well commented in consistent with the associated code. No additional commentary other than comments in the code will be marked. Include evidence, copied from the VHDL design tool that the code compiles successfully without errors. You should show well understanding of the code during presentation of the work. (30 Marks) Task 3 You are required to produce and insert here the test bench in VHDL applying all possible stimuli to the modeled device. It should be well commented in consistent with the associated code for all different test cases. No additional commentary other than comments in the code will be marked. Include evidence, copied from the VHDL design tool that the test bench compiles successfully without errors. You should show decent understanding of the code during presentation of the work. (20 Marks) Task 4 You are required to insert here a waveform covering all the features of functional model from the VHDL design tool to illustrate that the model works correctly for all test cases. Annotate comments on the waveform to explain all features for different test cases. Annotation should be consistent with simulation results. If you just supply a waveform without annotations marks will be deducted. Conciseness is important and ideally you will show your simulation on a single A4 page (landscape format suggested). Simulations longer than 3 A4 pages will not be marked. No commentary otherASIC Design-ELEC 30003-Spring-17-CW2-R-QP ELEC 30003 Page 3 of 5 than the annotations on the waveform will be marked. Take care when converting images to pdf format that the details of your simulation are clearly visible in the pdf document. (20 Marks) Task 5 You are required to practically demonstrate functional results covering all features of the design for all test cases on Altera DE2-115 target board with proper explanation and answering the questions raised by the instructor during demonstration of the work. Use pushbutton Key as a manual clock input. (20 Marks) Guidelines Follow the guidelines mentioned below for your assignment.  Assignment should be typed and an electronic copy is to be submitted through Moodle.  Handwritten assignments will not be accepted  Assignment should be complete and sign the cover sheet with the following information  Student name  Student ID  Assignment should be typed using Times New Roman font size 12.  You are encouraged to refer the books in Library or use internet resource or computer magazines or any other resource but you should not cut/copy and paste from internet.  Copy paste from the Internet is strictly not acceptable.  References should be included in the last page as follows. At least refer two international conference/journal paper to support your work and cite them.  Author name, Book Title, Publisher, Year in case of books.  In case of web site references type the full path of the web page with referenced date.  In case of magazines/ periodicals type article name, magazine name, Issue Number and date.  The report need to be uploaded to the “turnitin” software checker at least two days prior to report submission deadline. Plagiarism A. First offence of plagiarism a. If a student is caught first time in an act of plagiarism during his/her course of study in any assignment other than project work, the student will be allowed to re-submit theASIC Design-ELEC 30003-Spring-17-CW2-R-QP ELEC 30003 Page 4 of 5 assignment once, within a maximum period of one week. However, a penalty of deduction of 25% of the marks obtained for the resubmitted work will be imposed. b. Period of re-submission: The student will have to re-submit the work one week from the date he or she is advised to re-submit. c. If the re-submitted work is also detected to be plagiarized, then the work will be awarded a zero. d. Re-submission of the work beyond the maximum period of one week will not be accepted and the work will be awarded a zero. e. If the student fails the module and has a proven case of academic integrity violation in this module , the student is required to reregister the module f. If plagiarism is detected in Project work (Project 1, Project Planning and Project Design and Implementation) the above clauses (a,b,c,d) do not apply and the work will be summarily rejected. In these cases the student will be awarded a fail (F) grade and is required to re-register the module B. Second offence of plagiarism a. If any student is caught second time in an act of plagiarism during his/her course of study (in a subsequent semester), the student will directly be awarded zero for the work in which plagiarism is detected. In such cases, the student will not be allowed to re-submit the work. b. If the student fails the module and has a proven case of academic integrity violation in this module, the student is required to re-register the module C. Third Offence of plagiarism If any student is caught for the third time in an act of plagiarism during his/her course of study (in a subsequent semester), the student will be penalized with a fail in the module and shall be required to re-register the module. D. Fourth Offence of plagiarism If any student is caught for the fourth time in an act of plagiarism during his/her course of study (in a subsequent semester), he shall be suspended from the College for a period of one semester. E. Fifth offence of plagiarism If any student is caught for the fifth time in an act of plagiarism during his/her course of study (in a subsequent semester), he shall be expelled from the College Malpractice (MP) A. First offence of MP If a student is caught in an act of malpractice for an assessment component irrespective of coursework or end semester, the student shall fail the module and shall be required to reregister the module. B. Second Offence of MPASIC Design-ELEC 30003-Spring-17-CW2-R-QP ELEC 30003 Page 5 of 5 If a student is caught a second time in an act of malpractice for an assessment component irrespective of coursework or end semester (in a subsequent semester), the student shall be suspended for one semester from the College. C. Third Offence of MP If a student is caught a third time in an act of malpractice for an assessment component irrespective of coursework or end semester (in a subsequent semester), the student shall be expelled from the College. Other cases It denotes all other forms of academic misconduct including but not limited to ghostwriting, collusion, fabrication, falsification, unauthorized access to unseen examination papers and other academic and administrative documents/systems and aiding academic dishonesty/misconduct If a student commits an act of academic integrity violation whether defined as above as “other cases” or of a different nature, those cases shall also be forwarded to a departmental level committee set for the purpose .The committee shall investigate the case by means of a viva and/or a disciplinary hearing and shall take appropriate decision. Late submission The recommended practice at MEC is to set the cutoff time to 23:59 on the due date for all assessment submissions. As per the Assessment Policy at MEC, for any late submissions, a penalty of deduction of 5% of the marks obtained for the resubmitted work will be imposed for each working day following the last date of submission till the date of actual submission. Assessment documents submitted beyond a period of one week after the last date of submission will not be accepted and will be awarded a zero for that assessment. In cases where the submission has been delayed due to extenuating circumstances, the student may be permitted to submit the work without imposing the late submission policy stated above. The extended period of submission will be one week from the original last date of submission. In such cases, the student is expected to submit the supporting certificates on or before the original last date of submission of the assessment and the decision of extension rests with faculty responsible for the assessment .The late submission policy shall be applied if the student fails to submit the work within one week of the original last date of submission. Students may contact their teachers for clarification on specific details of the submission time if required.