Part 01 Answer the following in you lab/tute book. Clarify your answers with suitable examples. 1. Explain the twos complement notation for integer numbers. 2. What is the sign extension rule for twos complement numbers and when would you need to use it? 3. What does a twos complement operation performed on a twos complement number produce? [ Hint: consider positive and negative starting values] 4. Indicate two methods to perform the negation of a fixed length twos complement number. 5. Explain the difference between the twos complement representation of a number, and the twos complement of a number. 6. When does a twos complement of a number produce the same number in an n-bit number? 7. What is the benefit of using floating point number representation over integer representation? 8. What is an inherent problem when using floating point representation? 9. What is the benefit of using a biased exponent in floating point representation? 10. Why do we prefer the normalised form rather than the de-normalised form to represent floating point (binary) numbers? 11. Discuss the concept and use of guard bits. Justify their use. Part 02 Exercise 1 Sketch a typical von Neumann CPU structure. Identify all components, state their purpose, and describe their Von Neumann specific characteristics, if any. Exercise 2 Identify the roles performed by the various CPU registers. Exercise 3 Sketch a traditional single bus computer diagram. Clearly identify all components. Exercise 4 Sketch a multiple-bus computer diagram. Identify all parts. What is the benefit of using a multi-bus architecture, compared with single bus architecture? Exercise 5 In your own words explain the main characteristics of QPI, PCI and PCIe connection schemes. Exercise 6 Consider a hypothetical 32-bit microprocessor (CPU in a chip), which has a 32-bit address bus, and a 32-bit instruction composed of two fields: an op-code byte, followed by either immediate data or operand address. (a) Determine the maximum address space that this CPU can reach directly. (b) Discuss the impact on the system speed if the CPU has: (i) a 32-bit address bus and 16-bit data bus. (ii) a 16-bit address bus and 16-bit data bus. (iii) a 32-bit address bus and 32-bit data bus. (c) How many bits does this CPU require for the program counter/instruction pointer, and the instruction register? Justify your answer. Part 03 Exercise 1 Obtain the control word to perform the following micro-operations the CPU shown in slides 24 - 25, of the lecture slides i. R4 ¬ R4 OR R3 ii. R5 ¬ R5 + 1 iii. R1 ¬ R7 iv. Output ¬ R2 v. Output ¬ Input vi. R6 ¬ shal R3 vii. R7 ¬ 0 Part 04 Question 1 What is the overall function of a control unit? Question 2 What basic tasks does a control unit perform? Question 3 What is the relationship between computer instructions and micro-operations? Question 4 What are Horizontal and Vertical microinstructions? List their features. Question 5 Write the μ-op expressions for the following instructions: i. LD Acc ii. ST Acc iii. ADD #3,Acc iv. AND Acc, #128 Question 6 Referring to the information for the hypothetical CPU given in the lecture slides 23 - 25, describe a feasible implementation of the instruction sequence: LD R1, #7 LD R2, #3 MUL R1, R2, R1 ST [R3], R1 Verify your solution by proving the validity of the result Question 7 Week 5 lecture slide 21 shows a 2-bit ICC flag to identify the instruction cycle. Why don't we need such a flag in a μ-programmed control unit? Question 8 Design a micro-instruction format for a CPU that has 8 registers, 1 of which is used as the accumulator, and a single ALU which is able to perform 16 functions, namely, 8 arithmetic, 4 logic, and 4 shift operations. All CPU components are connected by internal system bus. Sketch diagram of your CPU architecture and your μ-instruction format to explain how the CPU operates. Part 05 Question 1 Explain why is a two stage pipeline unlikely to reduce the instruction cycle time by 50% in comparison to no pipeline usage? Question 2 List the approaches that an instruction pipeline can take to deal with conditional branches Question 3 List and briefly discuss the four ways which an execution pipeline can make branch predictions to deal with conditional branches. Question 4 List the typical characteristics of RISC architecture machines. Question 5 Identify typical distinguishing characteristics between RISC and CISC architecture and organisation. Question 6 Describe how data movement is minimised in RISC architecture to speed up operation in modular program design Part 06 Problem 1 Refer to the execution trace shown in part (a) of lecture slide 25. (a) Redraw the execution trace for the same instruction set for a CPU using: (i) no pipeline, and (ii) a two stage pipeline Briefly discuss your results. (b) Indicate whether your results support the premise stated in question 1. Justify your answer. Problem 2 Refer to the branch prediction state diagrams shown below. (a) Describe the prediction behaviour depicted in each state diagram. (b) Compare the behaviours depicted in the state diagrams. (c) Indicate the relative merits of each of the 3 approaches. Part 07 Question 1 What are the differences among sequential access, direct access, and random access memories? Question 2 Briefly describe the relationship among access time, cost, and capacity with reference to memory hierarchy. Question 3 In what two senses is the term random access memory used? Question 4 What are the differences between DRAM and SRAM? Compare their speed, size, and cost. Question 5 How does SDRAM differ from DRAM? Question 6 How does RDRAM differ from SDRAM? Question 7 Distinguish between CAV and CLV. Question 8 What is RAID? What common characteristics are shared by all levels of RAID? Question 9 Briefly describe the 7 RAID levels. Question 10 What is virtual memory? List a few advantages of virtual Memory. Question 11 What are the steps in virtual address translation? Question 12 With reference to virtual memory management, what is the difference between segmentation and pagination? Question 13 What is demand paging? List a few advantages for it. Question 14 With reference to caches, what are the differences among direct, associative and set associative mapping? Question 15 Discuss briefly, why it is possible to achieve a high hit rate with a relatively small amount of cache. Part 08 Question 1 How are parallel computer architectures classified based on Flynn's taxonomy? Give a brief explanation of each system type with a block diagram. Question 2 What is cache coherence? Question 3 Differentiate between multiprogramming and multiprocessing. Question 4 What are the main characteristics of an SMP, NUMA and Cluster system? Give their benefits. Question 5 What is CPU execution time? How can it be determined? Question 6 How can the performance of different computers be compared? Give your reasons for it. Question 7 What is MFLOPS? What is its significance? Question 8 What are benchmarks? What is its significance? List a few different benchmarks. Question 9 List a few methods to improve latency and bandwidth.